1. Field of the Invention
The invention relates to a semiconductor device and a method of manufacturing the same, and in particular relates to a semiconductor device having a field-effect transistor and a method of manufacturing the same.
2. Description of the Background Art
In recent years, demands for semiconductor devices have been rapidly increased owing to remarkable spread of information devices such as computers. In connection with functions, semiconductor devices having large storage capacities and capable of fast operation have been demanded. Accordingly, technical development has been made for improving the density or degree of integration, response and reliability of the semiconductor device.
Among the semiconductor devices, field-effect transistors have been used as components forming a dynamic random access memory and a static random access memory. The field-effect transistor has a gate electrode formed on a semiconductor substrate with a gate insulating film therebetween, and source and drain regions formed on the opposite sides of the gate electrode, respectively.
As the field-effect transistor is miniaturized for high-density integration, the channel length of the gate electrodes decreases. Recently, the channel length has been reduced to about 0.2 xcexcm. As the channel length decreases, the sectional area of the gate electrode decreases. This increases the electric resistance of the gate electrode. For suppressing increase of the electric resistance, field-effect transistors which employ gate electrodes made of metal have been used.
As compared with a gate electrode made of polycrystalline silicon, the gate electrode made of metal has a low thermal resistance. In a process of forming an interlayer insulating film after forming the gate electrode, therefore, disadvantages such as melting of the metal of the gate electrode occur due to a thermal treatment for forming the interlayer insulating film. Accordingly, a so-called replace gate process, in which the gate electrode is formed after forming the interlayer insulating film, is generally employed if the metal is used in the gate electrode.
Description will now be given on a field-effect transistor using metal in a gate electrode as well as a method of manufacturing it. FIG. 14 is a sectional view of a conventional semiconductor device using metal in the gate electrode. Referring to FIG. 14, an n-type source region 223s and an n-type drain region 223d spaced from each other are formed in a p-type semiconductor region of a silicon substrate 201. A gate electrode 240 located between source and drain regions 223s and 223d is formed on silicon substrate 201 with a gate insulating film 243 therebetween. Gate electrode 240 as well as source region 223s and drain region 223d form a field-effect transistor 200.
Source region 223s has a lightly doped impurity region 221s having a relatively low concentration of n-type impurity as well as a heavily doped impurity region 222s having a relatively high concentration of n-type impurity. Drain region 223d has a lightly doped impurity region 221d having a relatively low concentration n-type impurity as well as a heavily doped impurity region 222d having a relatively high concentration of n-type impurity. A p-type pocket region 211 is formed around lightly doped impurity region 221s. Also, p-type pocket region 211 is formed around lightly doped impurity region 221d. A counter dope region 228a which has a lower concentration of n-type impurity than source and drain regions 223s and 223d is formed between source and drain regions 223s and 223d, and is located near the surface of silicon substrate 201. A p-type channel dope region 212 is formed under counter dope region 228a. 
Gate electrode 240 formed of a barrier layer 241 and a metal layer 242 is formed on a main surface 201a of silicon substrate 201 with a gate insulating film 243 formed of a silicon oxide film therebetween. A side wall oxide film 231 is formed on a sidewall of gate electrode 240. Gate electrode 240 is covered with an interlayer insulating film 232. Metal layer 242 is made of, e.g., copper, and barrier layer 241 is made of, e.g., titanium nitride.
A method of manufacturing the semiconductor device shown in FIG. 14 will now be described. FIGS. 15-21 are sectional views showing the method of manufacturing the semiconductor device shown in FIG. 14. Referring to FIG. 15, thermal oxidization is performed to from gate insulating film 243 on main surface 201a of silicon substrate 201. CVD (Chemical Vapor Deposition) is performed to form a polycrystalline silicon layer 251 on gate insulating film 243. Resist is applied to polycrystalline silicon layer 251, and is patterned into a predetermined configuration to from a resist pattern 271.
Referring to FIG. 16, polycrystalline silicon layer 251 and gate insulating film 243 masked with resist pattern 271 are patterned into a predetermined configuration. Using polycrystalline silicon layer 251 thus patterned as a mask, impurity such as boron is implanted into silicon substrate 201 to form pocket region 211. Then, impurity such as arsenic is implanted into silicon substrate 201 in a direction indicated by arrows 252 so that lightly doped impurity regions 221s and 221d are formed.
Referring to FIG. 17, a silicon oxide film is formed over silicon substrate 201 and polycrystalline silicon layer 251. Etch-back is effected entirely on this silicon oxide film to form sidewall oxide film 231 on the sidewall of polycrystalline silicon layer 251. Using side wall oxide film 231 and polycrystalline silicon layer 251 as a mask, impurity such as arsenic is implanted into silicon substrate 201 in a direction indicated by arrows 253 so that heavily doped impurity regions 222s and 222d are formed.
Referring to FIG. 18, interlayer insulating film 232 covering silicon substrate 201 is formed and flattened by CMP (Chemical Mechanical Polishing) to expose the surface of polycrystalline silicon layer 251. Thereafter, polycrystalline silicon layer 251 is removed by chemical etching. Thereby, an aperture 233 is formed.
Referring to FIG. 19, impurity such as boron is implanted into silicon substrate 201, which is masked with interlayer insulating film 232 and side wall oxide film 231, through aperture 233 in a direction indicated by arrows 255. Thereby, channel dope region 212 is formed.
Referring to FIG. 20, impurity such as arsenic is implanted through aperture 233, which is masked with interlayer insulating film 232 and side wall oxide film 231, in a direction indicated by arrows 256. Thereby, counter dope region 228a is formed.
Referring to FIG. 21, barrier metal layer 241 and metal layer 242 which fill aperture 233 and cover interlayer insulating film 232 are formed, and are flattened, e.g., by CMP to form gate electrode 240 shown in FIG. 14.
In recent years, the semiconductor devices have been increasingly miniaturized to a higher extent and field-effect transistors of the foregoing type employ the gate electrodes having a channel length shorter than about 0.2 xcexcm. The field-effect transistor thus miniaturized suffers from several problems described below.
FIG. 22 shows problems which may arise in a conventional semiconductor device. Referring to FIG. 22, miniaturization of the semiconductor device causes variations in inner diameter (length) of aperture 233 used for forming the gate electrode. More specifically, the actual inner diameter of aperture 233 may deviate from a designed value, e.g., of 200 nm due to shift in position of the pattern in the patterning step. For example, even when each aperture 233 is designed to have an inner diameter equal to 200 xcexcm, aperture 233a may have a length of A41 equal to 180 xcexcm, and aperture 233b may have a length of A51 equal to 220 nm, as shown in FIG. 22. When there is a difference in size between apertures 233a and 233b, a difference occurs also in size between counter dope regions 228a and 228b, which are formed by implanting arsenic through apertures 233a and 233b in a direction of arrows 256, respectively. Counter dope region 228a has a length of 180 nm, and counter dope region 228b has a length of 220 nm.
A threshold voltage of field-effect transistor 200 shown in FIG. 14 depends on an impurity concentration of counter dope region 228a, a length A61 of counter dope region 228 and other factors. Counter dope regions 228a and 228b shown in FIG. 22 have the same impurity concentrations and different lengths, respectively. Therefore, the field-effect transistor having counter dope region 228a and the field-effect transistor having counter dope region 228b have different threshold voltages, respectively. More specifically, the field-effect transistor having shorter counter dope region 228a has a lower threshold voltage. The field-effect transistor having longer counter dope region 228b has a higher threshold voltage. As described above, if counter dope regions 228a and 228b have actual lengths shifted from the designed values, respectively, variations occur in threshold voltage among the plurality of field-effect transistors formed on the semiconductor substrate, and therefore the reliability of the semiconductor device decreases.
As shown in FIG. 14, pocket regions 211 and channel dope region 212 are formed between source and drain regions 223s and 223d for preventing punch-through. As the channel length decreases, the punch-through is more likely to occur. Therefore, the concentration of boron implanted into pocket region 211 and channel dope region 212 has been further increasing. Therefore, a high electric field occurs between n-type lightly doped impurity region 221d, which forms drain region 223d, and the opposed regions, i.e., pocket region 211 and channel dope region 212. When a high electric field occurs near drain region 223d, so-called hot carriers are produced so that the threshold voltage of the field-effect transistor varies, and the reliability decreases.
For overcoming the problems of hot carriers described above, such a manner has been employed in step shown in FIG. 16 that nitrogen is implanted into silicon substrate 201 in a direction indicated by arrows 252. If nitrogen atoms are present near an interface between silicon substrate 201 and gate insulating film 243, implantation of hot carriers into the insulating film is suppressed, and deterioration of the semiconductor device can be prevented.
However, the nitrogen implanted in the above step deactivates boron in pocket region 211 and a portion of channel dope region 212 near the gate end, and thereby the resistance against punch-through decreases. Further, the nitrogen moves into counter dope region 228a so that variations in threshold voltage and other disadvantages occur, resulting in lowering of the reliability.
Accordingly, the invention has been made for overcoming the above problems, and an object of the invention is to provide a semiconductor device, in which a channel length can be reduced without reducing reliability.
Another object of the invention is to provide a semiconductor device, in which variations in threshold voltage among a plurality of field-effect transistors can be prevented, and thereby high reliability can be achieved.
Still another aspect of the invention is to provide a semiconductor device, in which implantation of hot carriers in the vicinity of a drain region is suppressed so that high reliability is achieved.
A semiconductor device according to an aspect of the invention includes a semiconductor substrate having a semiconductor region of a first conductivity type, and a first field-effect transistor formed in the semiconductor region. The first field-effect transistor includes a first gate electrode, a pair of first source and drain regions, and a first channel region. The first gate electrode is formed on the semiconductor region with a gate insulating film therebetween. The pair of source and drain regions are formed in the semiconductor region and on the opposite sides of the first gate electrode, respectively, and contain impurity of a second conductivity type in a first concentration. The first channel region is formed in the semiconductor region and under the first gate electrode, is in contact with the first source and drain regions, and contains impurity of the second conductivity type in a second concentration lower than the first concentration. The first channel region includes a pair of first lightly doped impurity regions being in contact with the first source and drain regions, respectively, and having a relatively low concentration of impurity of the second conductivity type, and a first heavily doped impurity region located between the paired first lightly doped impurity regions, and having a relatively high concentration of impurity of the second conductivity type.
In the semiconductor device having the above structure, the first channel region includes the lightly doped impurity region and the heavily doped impurity region. Therefore, by appropriately setting a ratio between the lightly and heavily doped impurity regions, the threshold voltage of the field-effect transistor can be set to an appropriate value. For example, the threshold voltage can be increased by increasing the ratio of the lightly doped impurity region and decreasing the ratio of the heavily doped impurity region. Further, the threshold voltage of the field-effect transistor can be decreased by decreasing the ratio of the lightly doped impurity region and increasing the ratio of the heavily doped impurity region. In the case where a plurality of field-effect transistors are present, the ratios between the lightly and heavily doped impurity regions may be appropriately determined, whereby the plurality of field-effect transistors can have uniform threshold voltages.
Preferably, the semiconductor device further includes a second field-effect transistor formed in the semiconductor region. The second field-effect transistor includes a second gate electrode, a pair of second source and drain regions, and a second channel region. The second gate electrode is formed on the semiconductor region with a gate insulating film therebetween. The pair of second source and drain regions are formed in the semiconductor region and on the opposite sides of the second gate electrode, respectively, and include impurity of the second conductivity type in a third concentration. The second channel region is formed in the semiconductor region and under the second gate electrode, is in contact with the second source and drain regions, and includes impurity of the second conductivity type in a fourth concentration lower than the third concentration. The second channel region includes a pair of a second lightly doped impurity regions and a second heavily doped impurity region. The pair of second lightly doped impurity regions are in contact with the second source and drain regions, respectively, and have a relatively low concentration of impurity of the second conductivity type. The second heavily doped impurity region is located between the paired second lightly doped impurity regions, and has a relatively high concentration of impurity of the second conductivity type.
In the semiconductor device having the structure described above, the first channel region includes the first lightly doped impurity region and the first heavily doped impurity region, and the second channel region includes the second lightly doped impurity region and the second heavily doped impurity region. Therefore, the ratio between the heavily and lightly doped impurity regions can be appropriately determined in each of the channel regions. Thereby, the first and second field-effect transistors can have the same threshold voltages.
Preferably, the first gate electrode has a relatively- small length. The second gate electrode has a relatively large length. The first channel has a length A1. The first heavily doped impurity region has a length A2. The second channel region has a length A3 larger than length A1. The second heavily doped impurity region has a length A4. The lengths A1, A2, A3 and A4 satisfy a relationship of A4/A3 less than A2/A1.
A4/A3 represents a ratio of the length of the heavily doped impurity region in the second channel region, and A2/A1 represents a ratio of the length of the first heavily doped impurity region in the first channel region. Since the length A3 of the second channel region is larger than the length A1 of the first channel region, the channel length of the second field-effect transistor is larger than the channel length of the first field-effect transistor. However, the ratio A1/A3 of the second heavily doped impurity region in the second channel region is smaller than the ratio A2/A4 of the first heavily doped impurity region in the first channel region. Therefore, the second field-effect transistor has a larger channel length than the first field-effect transistor, and has the higher impurity concentration in the channel region so that the first and second field-effect transistors can have the substantially same threshold voltages.
Preferably, the first and second lightly doped impurity regions have the substantially equal lengths.
According to another aspect of the invention, a semiconductor device includes a semiconductor substrate having a semiconductor region of a p-type, and a field-effect transistor formed in the semiconductor region. The field-effect transistor includes a gate electrode, a pair of first impurity regions of an n-type, a second impurity region of the p-type, and a nitrogen region. The gate electrode is formed on the semiconductor region with a gate insulating film therebetween. The pair of first impurity regions of the n-type are formed in the semiconductor region and on the opposite sides of the gate electrode, respectively. The second impurity region of the p-type is formed in the semiconductor region, and is in contact with at least one of the first impurity regions. The nitrogen region is formed in the semiconductor region, has a high nitrogen concentration in the vicinity of a boundary between the second impurity region and at least one of the first impurity regions, and has a relatively low nitrogen concentration on a central side of the gate electrode.
In the semiconductor device having the structure described above, since the nitrogen concentration is high at the portion near the boundary between the second impurity region and one of the first impurity regions, implantation of hot carriers into an interlayer insulating film is suppressed in this portion so that deterioration of the semiconductor device can be suppressed. Since the nitrogen concentration is low on the central side of the gate electrode, deactivation of p-type impurity by the nitrogen can be prevented on the central side of the gate electrode. Accordingly, punch-through and others in this portion can be prevented. As a result, it is possible to provide the semiconductor device which can suppresses variations in threshold voltage, and has high reliability.
Preferably, one of the first impurity regions is a drain region. In this case, since generation of hot carriers can be prevented in the vicinity of the drain, the semiconductor device can have particularly high reliability.
According to still another aspect of the invention, a semiconductor device includes a semiconductor substrate having a semiconductor region of a first conductivity type, and a field-effect transistor formed in the semiconductor region. The field-effect transistor includes a gate electrode, a pair of first impurity regions, and a second impurity region. The gate electrode is formed on the semiconductor region with a gate insulating film therebetween. The pair of first impurity regions are formed in the semiconductor region and on the opposite sides of the gate electrode, respectively, and include impurity of a second conductivity type. The second impurity region is formed between the paired first impurity regions, and contains impurity of the first conductivity type. The second impurity region includes a lightly doped impurity region having a relatively low concentration of impurity of the first conductivity type, and located relatively close to one of the paired first impurity regions, and a heavily doped impurity region having a relatively high concentration of impurity of the first conductivity type, and being relatively remote from one of the paired first impurity regions.
In the semiconductor device having the above structure, the lightly doped impurity region having a low concentration of impurity of the first conductivity type is present in the position close to one of the first impurity regions containing the impurity of the second conductivity type. Therefore, a high electric field does not occur across this lightly doped impurity region and the first impurity region. As a result, generation of hot carriers can be prevented in this portion. Further, the heavily doped impurity region having a high concentration of impurity of the first conductivity type is present in a position remote from one of the first impurity regions. Therefore, punch-through between the paired first impurity regions can be prevented. As a result, the semiconductor device can have high reliability.
Preferably, one of the first impurity regions is a drain region.
In this case, since generation of hot carriers can be effectively prevented in the vicinity of the drain, it is possible to prevent the semiconductor device which can prevent variations in threshold voltage and others, and has high reliability.
A method of manufacturing a semiconductor device according to an aspect of the invention includes the following steps:
(1) Step of forming a pair of source and drain regions of a second conductivity type spaced from each other in a semiconductor region of a semiconductor substrate having a main surface and the semiconductor region of a first conductivity type.
(2) Step of forming on the semiconductor region an insulating layer provided with an aperture having a length of L and a depth of H, and reaching a portion of the semiconductor region between the paired source and drain regions.
(3) Step of implanting impurity of the second conductivity type through the aperture into the semiconductor region in directions directed from the source region toward the drain region and from the drain region toward the source region, respectively, at an angle xcex8 satisfying a relationship expressed by (8xc2x0xe2x89xa6xcex8xe2x89xa6tanxe2x88x921 (L/2H)) with respect to the main surface of the semiconductor substrate, and thereby forming a channel region including a pair of lightly doped impurity regions having a relatively low concentration of impurity of the second conductivity type and being in contact with the source and drain regions, respectively, and a heavily doped impurity region located between the paired lightly doped impurity regions and having a relatively high concentration of impurity of the second conductivity type.
(4) Step of forming a gate electrode filling the aperture and located on the semiconductor region with a gate insulating film therebetween.
According to the method of manufacturing the semiconductor device including the above steps, since the impurity of the second conductivity type is implanted twice into the central portion of the channel region, the heavily doped impurity region having a relatively high concentration of the impurity of the second conductivity type is formed. Further, the impurity of the second conductivity type is implanted only once into the peripheral portion of the channel region. Therefore, the lightly doped impurity region having a relatively low concentration of impurity of the second conductivity type is formed. As described above, the impurity of the second conductivity type is implanted in the directions forming the predetermined angle to the main surface of the semiconductor substrate, the lightly doped impurity region having a relatively low impurity concentration and the heavily doped impurity region having a relatively high impurity concentration can be formed in a self-aligning manner. As a result, it is possible to provide the semiconductor device allowing adjustment of the threshold voltage without particularly requiring an additional step.
According to another aspect of the invention, a method of manufacturing a semiconductor device includes the following steps:
(1) Step of forming a pair of first impurity regions of an n-type spaced from each other in a semiconductor region of a semiconductor substrate having a main surface and the semiconductor region of a p-type.
(2) Step of forming on the semiconductor region an insulating layer provided with an aperture having a length of L and a depth of H, and reaching a portion of the semiconductor region between the paired first impurity regions.
(3) Step of forming in the semiconductor region a second impurity region of the p-type being in contact with at least one of the first impurity regions.
(4) Step of implanting nitrogen through the aperture into the semiconductor region in a direction directed toward one of the paired first impurity regions from the other at an angle xcex8 satisfying a relationship expressed by (tanxe2x88x921 (L/2H)xe2x89xa6xcex8xe2x89xa6tanxe2x88x921 (L/H)) with respect to the main surface of the semiconductor substrate, and thereby forming a nitrogen region having a relatively high nitrogen concentration in the vicinity of a boundary between the second impurity region and one of the first impurity regions as well as a relatively low nitrogen concentration on the central side of the gate electrode.
(5) Step of forming a gate electrode filling the aperture and located on the semiconductor region with a gate insulating film therebetween.
According to the method of manufacturing the semiconductor device including the above steps, the nitrogen is implanted into the semiconductor region at the predetermined angle xcex8 with respect to the main surface of the semiconductor substrate. This forms the nitrogen region having the relatively high nitrogen concentration in the vicinity of the boundary between the second impurity region and one of the second impurity regions as well as the relatively low nitrogen concentration on the central side of the gate electrode. Since this nitrogen region has the high nitrogen concentration in the vicinity of the boundary between the second impurity region and one of the first impurity regions, generation of hot carriers is prevented. Since the nitrogen region has a low nitrogen concentration on the central side of the gate electrode, the p-type impurity in this central portion is not deactivated so that the punch-through resistance does not lower. According to the invention, therefore, it is possible to provide the semiconductor device having high reliability without particularly requiring an additional step.
According to still another aspect of the invention, a method of manufacturing a semiconductor device includes the following steps:
(1) Step of forming a pair of first impurity regions of a second conductivity type spaced from each other in a semiconductor region of a semiconductor substrate having a main surface and the semiconductor region of a first conductivity type.
(2) Step of forming on the semiconductor region an insulating layer provided with an aperture having a length of L and a depth of H, and reaching a portion of the semiconductor region between the paired first impurity regions.
(3) Step of implanting impurity of the first conductivity type through the aperture into the semiconductor region in a direction directed from one of the paired first impurity regions toward the other at an angle xcex8 satisfying a relationship expressed by (8xc2x0xe2x89xa6xcex8xe2x89xa6tanxe2x88x921 (L/2H)) with respect to the main surface of the semiconductor substrate, and thereby forming a second impurity region including a lightly doped impurity region having a relatively low concentration of impurity of the first conductivity type and located relatively close to one of the paired first impurity regions, and a heavily doped impurity region having a relatively high concentration of impurity of the first conductivity type and located relatively remote from one of the paired first impurity regions.
(4) Step of forming a gate electrode filling the aperture and located on the semiconductor region with a gate insulating film therebetween.
According to the method of manufacturing the semiconductor device described above, the second impurity region having the lightly and heavily doped impurity regions is formed in a self-aligning manner by implanting the impurity of the first conductivity type in a direction forming the angle xcex8 with respect to the main surface of the semiconductor substrate. Since the lightly doped impurity region having a relatively low concentration of impurity of the first conductivity type is formed in the portion near the first impurity region, occurrence of a high electric field can be prevented in the vicinity of the first impurity region. As a result, it is possible to provide the semiconductor device, in which hot carriers do not occur, and high reliability is ensured, without particularly requiring an additional step. Further, the heavily doped impurity region having a relatively high concentration of impurity of the first conductivity type is formed in a portion remote from one of the first impurity regions. Therefore, occurrence of punch-through can be prevented in this remote portion. As a result, it is possible to provide the semiconductor device having high reliability without particularly requiring an additional step.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.